1. Field of the Invention
The present invention generally relates to data communications, and more particularly, to a communications system that communicates both time division multiplexed data (synchronous data) and packet data (variable bit rate) on a shared bus.
2. Discussion of the Related Art
In recent years, there has been a notable migration of digital communications from time-division-multiplexed transmission systems to packet-based transmission systems. This migration has led to the development of communications equipment having the ability to communicate both types of digital transmissions.
In this regard, a communications device known as a xe2x80x9cnetwork access unitxe2x80x9d(NAU) or xe2x80x9cnetwork access switchxe2x80x9d (NAS) typically provides network switching services between multiple local and one or more network interfaces. Examples of local interfaces are RS232, DSX-1, EIA-530, etc. Examples of network interfaces are T1, T3, or SONET facilities. A network access unit provides transmission between multiple local communication networks, and a single network facility. The network access switch is a more general device, which provides communication between multiple local and network interfaces. The NAU typically resides at a home office, small office, branch office, or network edge. The NAS typically resides in the network cloud or at a large regional office fed by multiple branches.
To provide the most flexibility, it is preferable that the NAS/NAU support two types of data: synchronous TDM data and packet data. For example, the support of synchronous data provides the ability to make telephone (i.e., voice) calls, while the support of packet data provides access to public or private network packet services. However, the asynchronous nature of packet data at the logical level combined with the requirements of synchronous data causes design tradeoffs in both the complexity and cost of a NAS/NAU.
Network access switching requirements have progressed from providing TDM only type switching services, to packet only type switching services, to hybrid TDM/packet type switching services. The architecture of the NAS/NAU has evolved in order to support the more recent requirements for packet, and hybrid TDM/packet type services.
Early NAU/NAS architectures were based on a TDM bus architecture (See FIG. 1A). The TDM bus provides for static switching of synchronous traffic between multiple interface modules 110-1, 110-N. The TDM bus architecture is best suited for offering TDM services. The TDM bus design offers lowest complexity, a minimum and constant transmission delay, guaranteed network bandwidth, and provides a robust ability to switch reconfigurations. The TDM bus allows modules to exchange data based on time slots, which repeat over a fixed frame time. A synchronous data stream is transmitted over the bus by transmitting the required number of bits in each frame time to match the transmission rate of the synchronous data stream. For example, a synchronous data stream of 64 kbps transmits 8 bits across the TDM bus for an 8 KHz bus frame. The number of 64 kbps data streams that can be transmitted across the bus is a function of the bus speed (throughput). Transmission of data across the bus is controlled by a time slot map, which is typically resides in each of the modules. The time slot map defines the times when a pair of modules exchange data across the bus. Essentially two atomic operations are required in the pair of TDM modules to begin exchanging 64 kbps or nxc3x9764 kbps data (where n is an integer value). While the configuring of this channel affects the transmission of data for this channel until configuration is complete, traffic transmitted in other channels are not affected by the reconfiguration. The time slot maps are typically structured so that a single 64 kbps or nxc3x9764 kbps channel can be added or removed in the network access switch without corrupting or disrupting the transmission of other 64 kbps data streams in the system. The ability to add or remove connections without disrupting existing connections in the NAS is usually a critical service requirement for voice and data networks. Finally, traffic delay across the bus is largely defined by the bus frame rate. Minimizing the switching delay is often an important requirement for delay sensitive TDM traffic such as voice. Frame rates of 8 Khz are typical in TDM based systems resulting in traffic delays of 125 xcexcs to 250 xcexcs. While the TDM bus is ideally suited for the switching of TDM traffic in the NAS, the classical TDM bus is not suited for the switching of packet traffic.
TDM based network access switches were originally designed for switching voice traffic, and later used to switch data traffic. TDM switches required static connections to be provisioned for the switching of data traffic. The major consideration for data traffic is that it is typically bursty in nature. A high volume of traffic will flow for a short period of time followed by idle periods. The TDM bus does not provide the ability for traffic to be dynamically switched from one module to another module over the bus in time. For a given configuration, the same two TDM modules continue to exchange information during the same time slot, until a reconfiguration occurs. For example, packet traffic from packet module 1 may be switched to packet module 2 in one instant, and then switched to packet module 3 in the next instant. Another consideration for supporting data traffic is that the actual traffic flow and connections are typically highly bursty as well. One machine may be required to exchange data with several machines, requiring multiple static connections in the TDM NAS between the one machine and its peers. Transmission of packet type applications through a TDM NAS typically results in an over provisioning and hence under utilization of NAS bus bandwidth. While information within the packet itself could be used to indicate which of the destination modules on the bus should receive the traffic, the standard TDM bus provides no effective means to use this information.
In order to address the shortcomings and limitations of the TDM switch for packet applications, a new type of NAS emerged to better manage packet data communications. The packet data switch (see FIG. 1B), Frame Relay switch, and multi-protocol router type architectures, provide a more suitable means for switching of packet data traffic. These devices are based on a packet switching bus. The key attribute of the packet switching bus is that the data packet is prefixed with a switching or routing tag which includes an identifier or address which is used by the system to switch (or route) traffic to the intended destination bus module (and interface). Another key attribute is that the bus bandwidth is more dynamically shared between all the modules communicating over the bus. Modules 112-1, 12-n not requiring transmission across the bus during a particular time, allow the packet bus bandwidth to be dynamically allocated to modules requiring transmission. Some of the key elements in a packet switching architecture are dynamic allocation (or arbitration) of the bus bandwidth, formation and identification of packet addressing information, and identification of the beginning and end of a packet. While the packet bus is ideally suited for packet applications, it is not well suited for the switching of delay sensitive TDM traffic. First of all, since information is transmitted across the bus as packets, TDM data first must be accumulated into a packet before it can be transmitted across the bus. Packetization delay of TDM data is a function of the data rate and packet size. The larger the packet and lower the data rate, the larger the delay. A 64 kbps voice stream packetized into a 200 byte packet, incurs a 25 ms packetization delay, which is likely to exceed end-to-end network delay requirements. Further, packet traffic is bursty in nature. Consequently, switching delays across the bus may vary considerably based on traffic load. Not only does the bus latency add to the overall delay, but the delay variation additionally results in a longer play-out buffer on the receive side of the system, where the TDM traffic in the packet is converted back to a TDM format. The longer play-out buffer adds yet another component to the end-to-end network delay. Other possibilities include allowing the TDM traffic to be carried in a smaller data packet, and adding prioritization to the bus arbitration scheme giving preference to the delay sensitive TDM packets over the more delay tolerant data packets.
Other issues with packetization of TDM traffic is the higher cost and complexity of the synchronous interface modules. Forming the payload and header components of the packet, requires higher levels of processing and more buffering than is required for a TDM type bus architecture. The associated packet header required to transmit the TDM traffic across the bus to the required output port/connection adds overhead, resulting in a decrease in usable system bus bandwidth. This is even more so the case if small packets are employed to carry the TDM traffic.
A very prevalent NAS architecture emerging today employing small packets in order to minimize delay of TDM traffic is the xe2x80x9cfast packetxe2x80x9d or ATM type architecture (See FIG. 1C). ATM technology defines a 53 byte packet (cell) and is designed to provide switching of mixed voice/data traffic types. The ATM switch architecture supports the key attributes facilitating packet data communications, while addressing many of the delay issues associated with packetization and switching of voice. While ATM integrates voice and data traffic types, it does compromise on both throughput and delay. Throughput is reduced for data traffic due to carrying the larger packet in a series of smaller fixed sized packets (segments or cells). Not only is the ratio of payload to header (overhead) bytes reduced, the fixed size cell results in a padding overhead which can be rather significant. Small variable length packets can incur as much as 65% overhead when carried in a fixed size cell. Overhead of voice packets can also be high depending on delay requirements. Voice delay is typically higher than comparable TDM systems. Even though overhead and latency for ATM is higher than its TDM and packet predecessors, they are often down-played. Many ATM products often carry significantly higher system capacities, consequently the overhead becomes less an issue. While bandwidth may not be an issue in ATM switches, it is still an issue for network facilities. Network service providers are still attempting to squeeze every bit of usable bandwidth out of their network facilities to control network costs. Even with the positive view of ATM, the majority of voice traffic is still being carried over traditional TDM facilities, and there are new emerging standards for high speed packet transmission (full packets) which will ultimately compete with ATM. While there are numerous ATM NAS, and NAU type products being introduced into the market today, equipment costs are also a consideration. ATM switching technology is still more costly than its TDM and packet counterparts. While ATM technology advances to new levels of integration, there are still significant power, real estate, and component costs in adapting both TDM and packet data traffic types to the ATM format.
Another prior art approach (FIG. 2A) for integrating TDM/packet traffic is for an NAU utilizing a TDM multiple-access method for packet transmission on shared synchronous serial buses. In this approach multiple TDM and Packet application modules couple to a common TDM bus for communicating data to a Network Access Module. A portion of the TDM bus bandwidth is allocated for packet data and is treated as a multiple access packet channel. Packet modules gain access and share the packet channel using an arbitration method. In this regard, reference is made to FIGS. 2A-2C, which are figures from U.S. Pat. No. 5,719,858 to Moore (hereinafter xe2x80x9cMoorexe2x80x9d). Moore discloses a method for access arbitration to the packet bandwidth employing a counter which is controlled via a PREQ signal 312 is defined.
Moore also defines a method for determining when the bus is in use, and when a packet transfer is complete releasing the bus employing a PHOLD signal 311. This approach provides an efficient substrate for aggregating packet traffic over a TDM bus in a NAU. One of the advantages with this approach is that a centralized packet manager is not required. Packet processing and buffering is distributed in each of the Packet Application modules; these functions are not required in the Network Access Module. Packet sources share the allocated TDM bus bandwidth reserved for the packet channel, which maximizes bus efficiency. This approach offers modularity as well as other advantages.
While the architecture and method of Moore are well suited to a Network Access Unit (NAU), they are limited in fulfilling the requirements of the more general Network Access Switch (NAS). One of the fundamental differences between the NAU and NAS is in how the system is designed to allow modules to exchange data with each other in the system. In a NAU, the system is designed such that application modules only exchange data with the network access modules (and vice versa). This precludes configurations such as those where traffic entering each of three specific modules is to be switched to each of the others and other similar configurations, typical of an NAS. Another limitation is that in order for the NAU to not require buffering, the rate of the packet channel over the bus must be identical to the rate of the packet channel defined over the network access facility. While there are no issues with this being the bus speed of the packet channel when there is a single network facility, it is insufficient when used to support transmission of packet traffic over multiple network interfaces. An alternative approach would be to allow for multiple packet channels over the bus. Each packet channel would be specifically associated with a particular network access facility. While this approach may work, it would require the structures supporting the Packet/TDM interface to be duplicated for each supported packet channel. This is neither practical, cost-effective, nor scalable for a network access switch.
Another limitation of Moore is the shared serial bus architecture, which inherently limits the capacity of the system. As reported, shared serial buses with rates of 10-33 Mbps are feasible. This is fine for NAUs having 1 or few T1""s. This is insufficient for a T3 NAU, and grossly inadequate for a broadband NAS. Increases in the bus capacity also increase the complexity of the packet application modules, requiring larger time slot maps to couple to the TDM bus.
The most significant limitation of the Moore architecture is the requirement for each of the packet application modules to maintain a copy of the time slot map for coupling to the TDM bus. The time slot map in the packet application module defines which of the bus time slots are allocated to the shared packet channel. The time slot map defined to access the packet channel ends up being identical for all packet modules, since the packet channel is shared by all the packet modules. Requiring multiple copies of the time slot map in each of the modules affects the cost and the flexibility of the system. The cost of the time slot map in the packet module is a function of its size and dependent on the total number of time slots (ie. bandwidth) in the system. The higher the system bandwidth, the higher the cost for this function in each of the packet modules. Not only does it seem somewhat redundant to maintain the same time slot information in all of the modules, the usage of this map by the packet modules is solely to determine whether or not a time slot is allocated for packet transmission. The value of the time slot map for this purpose is seriously questioned as compared to the normal role performed by the time slot map in a TDM module. The time slot map of a TDM module is not only used to determine when a TDM module is to transmit data across the bus, it is also used to perform the switching function performed by the TDM module as TDM data is transmitted from its input port onto the bus.
An issue with maintaining identical copies of the time slot map in the packet modules is synchronization. Changes to the time slot maps in different packet modules such as adding or removing packet bandwidth, may disrupt or corrupt current packet data transmission. Each of the packet time slot maps must generally be updated at exactly the same instant in order to not disrupt packets currently being transmitted over the bus. In addition, failure to synchronize the time slot maps may also disrupt the logical functions associated with the packet processing or arbitration state machines. Inconsistent time slot maps may affect the reliability of the arbitration state machines of the different modules resulting in loss of synchronization if these issues are not specifically addressed. This type of coordination was not required for TDM channels over the TDM bus, since reconfiguration of a particular TDM channel does not affect other channels. This is only an issue for the packet type where multiple modules exchange data through a common set of time slots on the TDM bus. Increasing or decreasing the rate of the packet channel does affect the quality of data transmission if no explicit mechanisms are provided to coordinate the changing of the time slot maps. While the requirement for non-disruptive reconfiguration of the packet channel is not significant when there is a single packet channel being transmitted over a single network interface as in the NAU, this is a serious issue when packets are being switched between multiple network interfaces. The seriousness of the problem is even more greatly exacerbated, when packet traffic is disrupted due to requiring more TDM bandwidth. This is the case when 1 or more of the time slots allocated to the packet channel are reallocated to the TDM channel. Reducing the size of the packet channel to provide additional TDM channel disrupts (or corrupts) transmission of all the packet channels. The system and method of Moore do not address this system requirement.
While it is desirable to implement a common bus structure for the integration packet/TDM traffic within a NAS, the aforementioned methods present a number of system problems. These problems include maintaining low delay, guaranteed throughput for the TDM traffic, dynamic allocation of bandwidth for the packet traffic, low complexity, low bus overhead, and finally bus bandwidth or connection configuration changes which are non-disruptive to packet communications.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a method and apparatus for communicating both packet data and time division multiplexed (TDM) transmissions over a shared TDM bus.
In accordance with an aspect of a preferred embodiment, the data communications apparatus further includes a packet network interface module and a synchronous network interface module, both modules in communication with the shared data communication bus. The packet network interface module is configured for communication across a packet-based communication interface, while the synchronous interface module is configured for communication across a TDM-based communication interface. Since the apparatus includes a plurality of packet modules, a bus contention mechanism is provided for resolving simultaneous requests for access to/control of the bus by multiple packet modules. An innovative method of bus contention for the packet channel is described as the preferred embodiment, or may be implemented using a number of ways which are well known.
In accordance with another aspect of the present invention, a method is provided for communicating time division multiplexed data (TDM) and packet data over a shared bus. In accordance with a preferred embodiment, the method includes the steps of asserting a primary packet data transmission inhibit signal whenever TDM data transmissions are occurring over the shared bus and de-asserting the primary packet data transmission inhibit signal whenever no TDM data transmissions are occurring over the shared bus. The primary packet data transmission inhibit signal provides a synchronized indication to all packet modules as to when the system bus can be used for packet data. This synchronization signal eliminates the need for multiple static TDM time slot maps in each of the packet modules. Provision of a common simultaneous reference to all packet modules, enables the system bandwidth available for packet transmission to change without corrupting or disrupting the packet data. The preferred method further includes the step of allocating a portion of the shared bus data transmission bandwidth, to the transmission of TDM data. Finally, the preferred method includes the steps of inhibiting the communication of packet data over the shared bus when the primary packet data transmission inhibit signal is asserted, and permitting the communication of packet data over the shared bus (in the allocated portion of the data transmission bandwidth) when the primary packet data transmission inhibit signal is de-asserted.
In accordance a preferred embodiment, the method, further includes the step of transmitting time-division-multiplexed (TDM) data when the primary inhibit signal is asserted. In the preferred embodiment, TDM data is handled in a manner that is well knownxe2x80x94e.g., TDM data transmissions occur in defined time slots. Further still, the method arbitrates the bandwidth of the shared portion of the data transmission bandwidth between two or more packet modules. This step of arbitrating includes the step of resolving contentions between the two or more packet modules for simultaneous access to the shared bus. Arbitration, and signaling to all the packet interface modules as to when the packet bandwidth is being used to transmit a packet across the shared bus is regulated by the secondary inhibit signal. This signal is asserted by the packet transmitter to indicate a packet transmission across the bus. This signal is used by the packet receiver to identify the start and end of the packet. It is also used as an indication to the other packet modules that a packet transmission is in progress. The remaining packet modules use this signal to determine when the transmission has completed, and can begin contending for a new packet transmission.
In accordance with another aspect of the invention, a method communicates time division multiplexed data (TDM) and packet data over a shared bus by dedicating a portion of a data transmission bandwidth of the shared bus to TDM data transmission and allowing the remaining system bus bandwidth of the shared bus for packet data transmission. The method further operates by asserting a primary packet data transmission inhibit signal for each TDM data transmission occurring over the shared bus. This prevents or suspends the transmission of packet data for each bus time slot used for TDM data transmission. Packet data transmission proceeds during time slots not allocated for TDM transmission, as indicated when the primary packet data transmission inhibit signal is de-asserted. More specifically, this packet communication step further includes the steps of receiving a request to transmit packet data from a packet module, resolving any request contentions (if more than one packet module requests permission to transmit a data packet), granting access for one of the packet modules to the shared bus, monitoring the state of current packet transmission over the bus to determine when packet transmission has completed. Finally, evaluating the state of the secondary packet data transmission inhibit signal, for the purpose of regulating the transmission of the data packet over the shared bus.